Commit aba1a48c authored by Michael Niedermayer's avatar Michael Niedermayer

Merge commit 'b3267559'

* commit 'b3267559':
  arm: rename ARMVFP config symbol to VFP
Merged-by: 's avatarMichael Niedermayer <michaelni@gmx.at>
parents 89c8eaa3 b3267559
......@@ -70,7 +70,7 @@ config.h: .config
SUBDIR_VARS := CLEANFILES EXAMPLES FFLIBS HOSTPROGS TESTPROGS TOOLS \
HEADERS ARCH_HEADERS BUILT_HEADERS SKIPHEADERS \
ARMV5TE-OBJS ARMV6-OBJS ARMVFP-OBJS NEON-OBJS \
ARMV5TE-OBJS ARMV6-OBJS VFP-OBJS NEON-OBJS \
ALTIVEC-OBJS VIS-OBJS \
MMX-OBJS YASM-OBJS \
MIPSFPU-OBJS MIPSDSPR2-OBJS MIPSDSPR1-OBJS MIPS32R2-OBJS \
......
OBJS-$(HAVE_ARMV5TE) += $(ARMV5TE-OBJS) $(ARMV5TE-OBJS-yes)
OBJS-$(HAVE_ARMV6) += $(ARMV6-OBJS) $(ARMV6-OBJS-yes)
OBJS-$(HAVE_ARMVFP) += $(ARMVFP-OBJS) $(ARMVFP-OBJS-yes)
OBJS-$(HAVE_VFP) += $(VFP-OBJS) $(VFP-OBJS-yes)
OBJS-$(HAVE_NEON) += $(NEON-OBJS) $(NEON-OBJS-yes)
OBJS-$(HAVE_MIPSFPU) += $(MIPSFPU-OBJS) $(MIPSFPU-OBJS-yes)
......
......@@ -296,7 +296,7 @@ Optimization options (experts only):
--disable-armv5te disable armv5te optimizations
--disable-armv6 disable armv6 optimizations
--disable-armv6t2 disable armv6t2 optimizations
--disable-armvfp disable ARM VFP optimizations
--disable-vfp disable VFP optimizations
--disable-neon disable NEON optimizations
--disable-vis disable VIS optimizations
--disable-inline-asm disable use of inline assembler
......@@ -1241,8 +1241,8 @@ ARCH_EXT_LIST_ARM='
armv5te
armv6
armv6t2
armvfp
neon
vfp
vfpv3
'
......@@ -1551,9 +1551,9 @@ CMDLINE_APPEND="
armv5te_deps="arm"
armv6_deps="arm"
armv6t2_deps="arm"
armvfp_deps="arm"
neon_deps="arm"
vfpv3_deps="armvfp"
vfp_deps="arm"
vfpv3_deps="vfp"
map 'eval ${v}_inline_deps=inline_asm' $ARCH_EXT_LIST_ARM
......@@ -3493,8 +3493,8 @@ EOF
enabled armv5te && check_insn armv5te 'qadd r0, r0, r0'
enabled armv6 && check_insn armv6 'sadd16 r0, r0, r0'
enabled armv6t2 && check_insn armv6t2 'movt r0, #0'
enabled armvfp && check_insn armvfp 'fadds s0, s0, s0'
enabled neon && check_insn neon 'vadd.i16 q0, q0, q0'
enabled vfp && check_insn vfp 'fadds s0, s0, s0'
enabled vfpv3 && check_insn vfpv3 'vmov.f32 s0, #1.0'
map 'enabled_any ${v}_external ${v}_inline || disable $v' $ARCH_EXT_LIST_ARM
......@@ -4186,7 +4186,7 @@ if enabled arm; then
echo "ARMv5TE enabled ${armv5te-no}"
echo "ARMv6 enabled ${armv6-no}"
echo "ARMv6T2 enabled ${armv6t2-no}"
echo "ARM VFP enabled ${armvfp-no}"
echo "VFP enabled ${vfp-no}"
echo "NEON enabled ${neon-no}"
fi
if enabled mips; then
......
......@@ -48,9 +48,9 @@ ARMV6-OBJS += arm/dsputil_init_armv6.o \
arm/dsputil_armv6.o \
arm/simple_idct_armv6.o \
ARMVFP-OBJS-$(HAVE_ARMV6) += arm/fmtconvert_vfp.o
VFP-OBJS-$(HAVE_ARMV6) += arm/fmtconvert_vfp.o
ARMVFP-OBJS += arm/dsputil_vfp.o \
VFP-OBJS += arm/dsputil_vfp.o \
arm/dsputil_init_vfp.o \
NEON-OBJS-$(CONFIG_FFT) += arm/fft_neon.o \
......
OBJS += arm/cpu.o \
arm/float_dsp_init_arm.o \
ARMVFP-OBJS += arm/float_dsp_init_vfp.o \
VFP-OBJS += arm/float_dsp_init_vfp.o \
arm/float_dsp_vfp.o \
NEON-OBJS += arm/float_dsp_init_neon.o \
......
......@@ -46,7 +46,7 @@
#if HAVE_NEON
.fpu neon
#elif HAVE_ARMVFP
#elif HAVE_VFP
.fpu vfp
#endif
......
......@@ -24,7 +24,7 @@ int ff_get_cpu_flags_arm(void)
return AV_CPU_FLAG_ARMV5TE * HAVE_ARMV5TE |
AV_CPU_FLAG_ARMV6 * HAVE_ARMV6 |
AV_CPU_FLAG_ARMV6T2 * HAVE_ARMV6T2 |
AV_CPU_FLAG_VFP * HAVE_ARMVFP |
AV_CPU_FLAG_VFP * HAVE_VFP |
AV_CPU_FLAG_VFPV3 * HAVE_VFPV3 |
AV_CPU_FLAG_NEON * HAVE_NEON;
}
......@@ -25,7 +25,7 @@
#define have_armv5te(flags) (HAVE_ARMV5TE && ((flags) & AV_CPU_FLAG_ARMV5TE))
#define have_armv6(flags) (HAVE_ARMV6 && ((flags) & AV_CPU_FLAG_ARMV6))
#define have_armv6t2(flags) (HAVE_ARMV6T2 && ((flags) & AV_CPU_FLAG_ARMV6T2))
#define have_vfp(flags) (HAVE_ARMVFP && ((flags) & AV_CPU_FLAG_VFP))
#define have_vfp(flags) (HAVE_VFP && ((flags) & AV_CPU_FLAG_VFP))
#define have_vfpv3(flags) (HAVE_VFPV3 && ((flags) & AV_CPU_FLAG_VFPV3))
#define have_neon(flags) (HAVE_NEON && ((flags) & AV_CPU_FLAG_NEON))
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment