Commit 8af3ce53 authored by Shivraj Patil's avatar Shivraj Patil Committed by Michael Niedermayer

configure: add support for mips32r5, p5600 cpu and msa

Imagination Technologies has come up with MIPS Warrior Processor Cores.
More details can be found at-
http://www.imgtec.com/mips/warrior/pclass.asp
http://www.imgtec.com/mips/warrior/iclass.asp

This is a preparation patch to submit optimized code for MSA (MIPS-SIMD-Architecture)
This patch set is adding support for P5600 and I6400 CPUs.

MIPS 'generic' case is added, with mips32r2 arch as default (fpu and dsp opt enabled).

Sample configurations for new MSA architectures-
    $ ./configure --enable-cross-compile --cross-prefix=<PATH> --arch=mips --target-os=linux --cpu=p5600
    $ ./configure --enable-cross-compile --cross-prefix=<PATH> --arch=mips --target-os=linux --cpu=i6400
Signed-off-by: 's avatarShivraj Patil <shivraj.patil@imgtec.com>
Reviewed-by: 's avatarNedeljko Babic <Nedeljko.Babic@imgtec.com>
Signed-off-by: 's avatarMichael Niedermayer <michaelni@gmx.at>
parent 599dc8fe
...@@ -360,8 +360,10 @@ Optimization options (experts only): ...@@ -360,8 +360,10 @@ Optimization options (experts only):
--disable-neon disable NEON optimizations --disable-neon disable NEON optimizations
--disable-inline-asm disable use of inline assembly --disable-inline-asm disable use of inline assembly
--disable-yasm disable use of nasm/yasm assembly --disable-yasm disable use of nasm/yasm assembly
--disable-mips32r5 disable MIPS32R5 optimizations
--disable-mipsdspr1 disable MIPS DSP ASE R1 optimizations --disable-mipsdspr1 disable MIPS DSP ASE R1 optimizations
--disable-mipsdspr2 disable MIPS DSP ASE R2 optimizations --disable-mipsdspr2 disable MIPS DSP ASE R2 optimizations
--disable-msa disable MSA optimizations
--disable-mipsfpu disable floating point MIPS optimizations --disable-mipsfpu disable floating point MIPS optimizations
--disable-fast-unaligned consider unaligned accesses slow --disable-fast-unaligned consider unaligned accesses slow
...@@ -1565,8 +1567,10 @@ ARCH_EXT_LIST_ARM=" ...@@ -1565,8 +1567,10 @@ ARCH_EXT_LIST_ARM="
ARCH_EXT_LIST_MIPS=" ARCH_EXT_LIST_MIPS="
mipsfpu mipsfpu
mips32r2 mips32r2
mips32r5
mipsdspr1 mipsdspr1
mipsdspr2 mipsdspr2
msa
" "
ARCH_EXT_LIST_X86_SIMD=" ARCH_EXT_LIST_X86_SIMD="
...@@ -2009,6 +2013,8 @@ map 'eval ${v}_inline_deps=inline_asm' $ARCH_EXT_LIST_ARM ...@@ -2009,6 +2013,8 @@ map 'eval ${v}_inline_deps=inline_asm' $ARCH_EXT_LIST_ARM
mipsfpu_deps="mips" mipsfpu_deps="mips"
mipsdspr1_deps="mips" mipsdspr1_deps="mips"
mipsdspr2_deps="mips" mipsdspr2_deps="mips"
mips32r5_deps="mips"
msa_deps="mips"
altivec_deps="ppc" altivec_deps="ppc"
ppc4xx_deps="ppc" ppc4xx_deps="ppc"
...@@ -3842,23 +3848,43 @@ elif enabled mips; then ...@@ -3842,23 +3848,43 @@ elif enabled mips; then
case $cpu in case $cpu in
24kc) 24kc)
disable mips32r5
disable mipsfpu disable mipsfpu
disable mipsdspr1 disable mipsdspr1
disable mipsdspr2 disable mipsdspr2
disable msa
;; ;;
24kf*) 24kf*)
disable mips32r5
disable mipsdspr1 disable mipsdspr1
disable mipsdspr2 disable mipsdspr2
disable msa
;; ;;
24kec|34kc|1004kc) 24kec|34kc|1004kc)
disable mips32r5
disable mipsfpu disable mipsfpu
disable mipsdspr2 disable mipsdspr2
disable msa
;; ;;
24kef*|34kf*|1004kf*) 24kef*|34kf*|1004kf*)
disable mips32r5
disable mipsdspr2 disable mipsdspr2
disable msa
;; ;;
74kc) 74kc)
disable mips32r5
disable mipsfpu disable mipsfpu
disable msa
;;
p5600)
disable mipsdspr1
disable mipsdspr2
check_cflags "-mtune=p5600"
;;
generic)
disable mips32r5
disable msa
;; ;;
esac esac
...@@ -4613,17 +4639,28 @@ elif enabled mips; then ...@@ -4613,17 +4639,28 @@ elif enabled mips; then
elif enabled mips64 && enabled mipsfpu; then elif enabled mips64 && enabled mipsfpu; then
add_cflags "-mips64" add_cflags "-mips64"
add_asflags "-mips64" add_asflags "-mips64"
elif enabled mipsfpu || enabled mipsdspr1 || enabled mipsdspr2; then elif enabled mipsdspr1 || enabled mipsdspr2; then
add_cflags "-mips32r2" add_cflags "-mips32r2 -mfp32"
add_asflags "-mips32r2" add_asflags "-mips32r2 -mfp32"
elif enabled mips32r5; then
check_cflags "-mfp64"
check_ldflags "-mfp64"
fi fi
enabled mips32r5 && check_cflags "-mips32r5 -msched-weight -mload-store-pairs -funroll-loops" &&
check_ldflags "-mips32r5" &&
check_inline_asm mips32r5 '"ulw $t0, ($t1)"'
enabled mipsdspr1 && add_cflags "-mdsp" && add_asflags "-mdsp" && enabled mipsdspr1 && add_cflags "-mdsp" && add_asflags "-mdsp" &&
check_inline_asm mipsdspr1 '"addu.qb $t0, $t1, $t2"' check_inline_asm mipsdspr1 '"addu.qb $t0, $t1, $t2"'
enabled mipsdspr2 && add_cflags "-mdspr2" && add_asflags "-mdspr2" && enabled mipsdspr2 && add_cflags "-mdspr2" && add_asflags "-mdspr2" &&
check_inline_asm mipsdspr2 '"absq_s.qb $t0, $t1"' check_inline_asm mipsdspr2 '"absq_s.qb $t0, $t1"'
enabled mipsfpu && add_cflags "-mhard-float" && add_asflags "-mhard-float" && enabled mipsfpu && add_cflags "-mhard-float" && add_asflags "-mhard-float" &&
check_inline_asm mipsfpu '"madd.d $f0, $f2, $f4, $f6"' check_inline_asm mipsfpu '"madd.d $f0, $f2, $f4, $f6"'
enabled msa && check_cflags "-mmsa" && check_ldflags "-mmsa" &&
check_inline_asm msa '"addvi.b $w0, $w1, 1"'
enabled mips32r5 && add_asflags "-mips32r5 -mfp64"
enabled msa && add_asflags "-mmsa"
elif enabled parisc; then elif enabled parisc; then
...@@ -5583,8 +5620,10 @@ if enabled arm; then ...@@ -5583,8 +5620,10 @@ if enabled arm; then
fi fi
if enabled mips; then if enabled mips; then
echo "MIPS FPU enabled ${mipsfpu-no}" echo "MIPS FPU enabled ${mipsfpu-no}"
echo "MIPS32R5 enabled ${mips32r5-no}"
echo "MIPS DSP R1 enabled ${mipsdspr1-no}" echo "MIPS DSP R1 enabled ${mipsdspr1-no}"
echo "MIPS DSP R2 enabled ${mipsdspr2-no}" echo "MIPS DSP R2 enabled ${mipsdspr2-no}"
echo "MIPS MSA enabled ${msa-no}"
fi fi
if enabled ppc; then if enabled ppc; then
echo "AltiVec enabled ${altivec-no}" echo "AltiVec enabled ${altivec-no}"
......
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