Skip to content

F
ffmpeg.wasm-core
Commit 7e3208a0 authored by Mans Rullgard's avatar Mans Rullgard Committed by Michael Niedermayer
Browse files
Options

ARM: libswresample: NEON optimised generic fltp to s16 conversion 

Adapted to swr by: Michael Niedermayer <michaelni@gmx.at>
Signed-off-by: 's avatarMichael Niedermayer <michaelni@gmx.at>
parent 97599f8c
Show whitespace changes
Inline Side-by-side
Showing with 242 additions and 0 deletions
libswresample/arm/audio_convert_init.c
View file @ 7e3208a0
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
void swri_oldapi_conv_flt_to_s16_neon(int16_t *dst, const float *src, int len); void swri_oldapi_conv_flt_to_s16_neon(int16_t *dst, const float *src, int len);
void swri_oldapi_conv_fltp_to_s16_2ch_neon(int16_t *dst, float *const *src, int len, int channels); void swri_oldapi_conv_fltp_to_s16_2ch_neon(int16_t *dst, float *const *src, int len, int channels);
void swri_oldapi_conv_fltp_to_s16_nch_neon(int16_t *dst, float *const *src, int len, int channels);
static void conv_flt_to_s16_neon(uint8_t **dst, const uint8_t **src, int len){ static void conv_flt_to_s16_neon(uint8_t **dst, const uint8_t **src, int len){
swri_oldapi_conv_flt_to_s16_neon((int16_t*)*dst, (const float*)*src, len); swri_oldapi_conv_flt_to_s16_neon((int16_t*)*dst, (const float*)*src, len);
...@@ -37,6 +38,12 @@ static void conv_fltp_to_s16_2ch_neon(uint8_t **dst, const uint8_t **src, int le ...@@ -37,6 +38,12 @@ static void conv_fltp_to_s16_2ch_neon(uint8_t **dst, const uint8_t **src, int le
swri_oldapi_conv_fltp_to_s16_2ch_neon((int16_t*)*dst, (float *const*)src, len, 2); swri_oldapi_conv_fltp_to_s16_2ch_neon((int16_t*)*dst, (float *const*)src, len, 2);
} }
static void conv_fltp_to_s16_nch_neon(uint8_t **dst, const uint8_t **src, int len){
int channels;
for(channels=3; channels<SWR_CH_MAX && src[channels]; channels++)
;
swri_oldapi_conv_fltp_to_s16_nch_neon((int16_t*)*dst, (float *const*)src, len, channels);
}
av_cold void swri_audio_convert_init_arm(struct AudioConvert *ac, av_cold void swri_audio_convert_init_arm(struct AudioConvert *ac,
enum AVSampleFormat out_fmt, enum AVSampleFormat out_fmt,
...@@ -52,5 +59,7 @@ av_cold void swri_audio_convert_init_arm(struct AudioConvert *ac, ...@@ -52,5 +59,7 @@ av_cold void swri_audio_convert_init_arm(struct AudioConvert *ac,
ac->simd_f = conv_flt_to_s16_neon; ac->simd_f = conv_flt_to_s16_neon;
if(out_fmt == AV_SAMPLE_FMT_S16 && in_fmt == AV_SAMPLE_FMT_FLTP && channels == 2) if(out_fmt == AV_SAMPLE_FMT_S16 && in_fmt == AV_SAMPLE_FMT_FLTP && channels == 2)
ac->simd_f = conv_fltp_to_s16_2ch_neon; ac->simd_f = conv_fltp_to_s16_2ch_neon;
if(out_fmt == AV_SAMPLE_FMT_S16 && in_fmt == AV_SAMPLE_FMT_FLTP && channels > 2)
ac->simd_f = conv_fltp_to_s16_nch_neon;
} }
} }
libswresample/arm/audio_convert_neon.S
View file @ 7e3208a0
...@@ -128,3 +128,236 @@ function swri_oldapi_conv_fltp_to_s16_2ch_neon, export=1 ...@@ -128,3 +128,236 @@ function swri_oldapi_conv_fltp_to_s16_2ch_neon, export=1
vst1.16 {q10-q11},[r0,:128]! vst1.16 {q10-q11},[r0,:128]!
bx lr bx lr
endfunc endfunc
function swri_oldapi_conv_fltp_to_s16_nch_neon, export=1
cmp r3, #2
itt lt
ldrlt r1, [r1]
blt swri_oldapi_conv_flt_to_s16_neon
beq swri_oldapi_conv_fltp_to_s16_2ch_neon
push {r4-r8, lr}
cmp r3, #4
lsl r12, r3, #1
blt 4f
@ 4 channels
5: ldm r1!, {r4-r7}
mov lr, r2
mov r8, r0
vld1.32 {q8}, [r4,:128]!
vcvt.s32.f32 q8, q8, #31
vld1.32 {q9}, [r5,:128]!
vcvt.s32.f32 q9, q9, #31
vld1.32 {q10}, [r6,:128]!
vcvt.s32.f32 q10, q10, #31
vld1.32 {q11}, [r7,:128]!
vcvt.s32.f32 q11, q11, #31
6: subs lr, lr, #8
vld1.32 {q0}, [r4,:128]!
vcvt.s32.f32 q0, q0, #31
vsri.32 q9, q8, #16
vld1.32 {q1}, [r5,:128]!
vcvt.s32.f32 q1, q1, #31
vsri.32 q11, q10, #16
vld1.32 {q2}, [r6,:128]!
vcvt.s32.f32 q2, q2, #31
vzip.32 d18, d22
vld1.32 {q3}, [r7,:128]!
vcvt.s32.f32 q3, q3, #31
vzip.32 d19, d23
vst1.16 {d18}, [r8], r12
vsri.32 q1, q0, #16
vst1.16 {d22}, [r8], r12
vsri.32 q3, q2, #16
vst1.16 {d19}, [r8], r12
vzip.32 d2, d6
vst1.16 {d23}, [r8], r12
vzip.32 d3, d7
beq 7f
vld1.32 {q8}, [r4,:128]!
vcvt.s32.f32 q8, q8, #31
vst1.16 {d2}, [r8], r12
vld1.32 {q9}, [r5,:128]!
vcvt.s32.f32 q9, q9, #31
vst1.16 {d6}, [r8], r12
vld1.32 {q10}, [r6,:128]!
vcvt.s32.f32 q10, q10, #31
vst1.16 {d3}, [r8], r12
vld1.32 {q11}, [r7,:128]!
vcvt.s32.f32 q11, q11, #31
vst1.16 {d7}, [r8], r12
b 6b
7: vst1.16 {d2}, [r8], r12
vst1.16 {d6}, [r8], r12
vst1.16 {d3}, [r8], r12
vst1.16 {d7}, [r8], r12
subs r3, r3, #4
it eq
popeq {r4-r8, pc}
cmp r3, #4
add r0, r0, #8
bge 5b
@ 2 channels
4: cmp r3, #2
blt 4f
ldm r1!, {r4-r5}
mov lr, r2
mov r8, r0
tst lr, #8
vld1.32 {q8}, [r4,:128]!
vcvt.s32.f32 q8, q8, #31
vld1.32 {q9}, [r5,:128]!
vcvt.s32.f32 q9, q9, #31
vld1.32 {q10}, [r4,:128]!
vcvt.s32.f32 q10, q10, #31
vld1.32 {q11}, [r5,:128]!
vcvt.s32.f32 q11, q11, #31
beq 6f
subs lr, lr, #8
beq 7f
vsri.32 d18, d16, #16
vsri.32 d19, d17, #16
vld1.32 {q8}, [r4,:128]!
vcvt.s32.f32 q8, q8, #31
vst1.32 {d18[0]}, [r8], r12
vsri.32 d22, d20, #16
vst1.32 {d18[1]}, [r8], r12
vsri.32 d23, d21, #16
vst1.32 {d19[0]}, [r8], r12
vst1.32 {d19[1]}, [r8], r12
vld1.32 {q9}, [r5,:128]!
vcvt.s32.f32 q9, q9, #31
vst1.32 {d22[0]}, [r8], r12
vst1.32 {d22[1]}, [r8], r12
vld1.32 {q10}, [r4,:128]!
vcvt.s32.f32 q10, q10, #31
vst1.32 {d23[0]}, [r8], r12
vst1.32 {d23[1]}, [r8], r12
vld1.32 {q11}, [r5,:128]!
vcvt.s32.f32 q11, q11, #31
6: subs lr, lr, #16
vld1.32 {q0}, [r4,:128]!
vcvt.s32.f32 q0, q0, #31
vsri.32 d18, d16, #16
vld1.32 {q1}, [r5,:128]!
vcvt.s32.f32 q1, q1, #31
vsri.32 d19, d17, #16
vld1.32 {q2}, [r4,:128]!
vcvt.s32.f32 q2, q2, #31
vld1.32 {q3}, [r5,:128]!
vcvt.s32.f32 q3, q3, #31
vst1.32 {d18[0]}, [r8], r12
vsri.32 d22, d20, #16
vst1.32 {d18[1]}, [r8], r12
vsri.32 d23, d21, #16
vst1.32 {d19[0]}, [r8], r12
vsri.32 d2, d0, #16
vst1.32 {d19[1]}, [r8], r12
vsri.32 d3, d1, #16
vst1.32 {d22[0]}, [r8], r12
vsri.32 d6, d4, #16
vst1.32 {d22[1]}, [r8], r12
vsri.32 d7, d5, #16
vst1.32 {d23[0]}, [r8], r12
vst1.32 {d23[1]}, [r8], r12
beq 6f
vld1.32 {q8}, [r4,:128]!
vcvt.s32.f32 q8, q8, #31
vst1.32 {d2[0]}, [r8], r12
vst1.32 {d2[1]}, [r8], r12
vld1.32 {q9}, [r5,:128]!
vcvt.s32.f32 q9, q9, #31
vst1.32 {d3[0]}, [r8], r12
vst1.32 {d3[1]}, [r8], r12
vld1.32 {q10}, [r4,:128]!
vcvt.s32.f32 q10, q10, #31
vst1.32 {d6[0]}, [r8], r12
vst1.32 {d6[1]}, [r8], r12
vld1.32 {q11}, [r5,:128]!
vcvt.s32.f32 q11, q11, #31
vst1.32 {d7[0]}, [r8], r12
vst1.32 {d7[1]}, [r8], r12
bgt 6b
6: vst1.32 {d2[0]}, [r8], r12
vst1.32 {d2[1]}, [r8], r12
vst1.32 {d3[0]}, [r8], r12
vst1.32 {d3[1]}, [r8], r12
vst1.32 {d6[0]}, [r8], r12
vst1.32 {d6[1]}, [r8], r12
vst1.32 {d7[0]}, [r8], r12
vst1.32 {d7[1]}, [r8], r12
b 8f
7: vsri.32 d18, d16, #16
vsri.32 d19, d17, #16
vst1.32 {d18[0]}, [r8], r12
vsri.32 d22, d20, #16
vst1.32 {d18[1]}, [r8], r12
vsri.32 d23, d21, #16
vst1.32 {d19[0]}, [r8], r12
vst1.32 {d19[1]}, [r8], r12
vst1.32 {d22[0]}, [r8], r12
vst1.32 {d22[1]}, [r8], r12
vst1.32 {d23[0]}, [r8], r12
vst1.32 {d23[1]}, [r8], r12
8: subs r3, r3, #2
add r0, r0, #4
it eq
popeq {r4-r8, pc}
@ 1 channel
4: ldr r4, [r1]
tst r2, #8
mov lr, r2
mov r5, r0
vld1.32 {q0}, [r4,:128]!
vcvt.s32.f32 q0, q0, #31
vld1.32 {q1}, [r4,:128]!
vcvt.s32.f32 q1, q1, #31
bne 8f
6: subs lr, lr, #16
vld1.32 {q2}, [r4,:128]!
vcvt.s32.f32 q2, q2, #31
vld1.32 {q3}, [r4,:128]!
vcvt.s32.f32 q3, q3, #31
vst1.16 {d0[1]}, [r5,:16], r12
vst1.16 {d0[3]}, [r5,:16], r12
vst1.16 {d1[1]}, [r5,:16], r12
vst1.16 {d1[3]}, [r5,:16], r12
vst1.16 {d2[1]}, [r5,:16], r12
vst1.16 {d2[3]}, [r5,:16], r12
vst1.16 {d3[1]}, [r5,:16], r12
vst1.16 {d3[3]}, [r5,:16], r12
beq 7f
vld1.32 {q0}, [r4,:128]!
vcvt.s32.f32 q0, q0, #31
vld1.32 {q1}, [r4,:128]!
vcvt.s32.f32 q1, q1, #31
7: vst1.16 {d4[1]}, [r5,:16], r12
vst1.16 {d4[3]}, [r5,:16], r12
vst1.16 {d5[1]}, [r5,:16], r12
vst1.16 {d5[3]}, [r5,:16], r12
vst1.16 {d6[1]}, [r5,:16], r12
vst1.16 {d6[3]}, [r5,:16], r12
vst1.16 {d7[1]}, [r5,:16], r12
vst1.16 {d7[3]}, [r5,:16], r12
bgt 6b
pop {r4-r8, pc}
8: subs lr, lr, #8
vst1.16 {d0[1]}, [r5,:16], r12
vst1.16 {d0[3]}, [r5,:16], r12
vst1.16 {d1[1]}, [r5,:16], r12
vst1.16 {d1[3]}, [r5,:16], r12
vst1.16 {d2[1]}, [r5,:16], r12
vst1.16 {d2[3]}, [r5,:16], r12
vst1.16 {d3[1]}, [r5,:16], r12
vst1.16 {d3[3]}, [r5,:16], r12
it eq
popeq {r4-r8, pc}
vld1.32 {q0}, [r4,:128]!
vcvt.s32.f32 q0, q0, #31
vld1.32 {q1}, [r4,:128]!
vcvt.s32.f32 q1, q1, #31
b 6b
endfunc
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment