Commit 1e477a97 authored by Rodger Combs's avatar Rodger Combs

lavu: add AESNI CPU flag

parent 057ce755
...@@ -368,6 +368,7 @@ Optimization options (experts only): ...@@ -368,6 +368,7 @@ Optimization options (experts only):
--disable-fma3 disable FMA3 optimizations --disable-fma3 disable FMA3 optimizations
--disable-fma4 disable FMA4 optimizations --disable-fma4 disable FMA4 optimizations
--disable-avx2 disable AVX2 optimizations --disable-avx2 disable AVX2 optimizations
--disable-aesni disable AESNI optimizations
--disable-armv5te disable armv5te optimizations --disable-armv5te disable armv5te optimizations
--disable-armv6 disable armv6 optimizations --disable-armv6 disable armv6 optimizations
--disable-armv6t2 disable armv6t2 optimizations --disable-armv6t2 disable armv6t2 optimizations
...@@ -1635,6 +1636,7 @@ ARCH_EXT_LIST_LOONGSON=" ...@@ -1635,6 +1636,7 @@ ARCH_EXT_LIST_LOONGSON="
" "
ARCH_EXT_LIST_X86_SIMD=" ARCH_EXT_LIST_X86_SIMD="
aesni
amd3dnow amd3dnow
amd3dnowext amd3dnowext
avx avx
...@@ -2128,6 +2130,7 @@ sse3_deps="sse2" ...@@ -2128,6 +2130,7 @@ sse3_deps="sse2"
ssse3_deps="sse3" ssse3_deps="sse3"
sse4_deps="ssse3" sse4_deps="ssse3"
sse42_deps="sse4" sse42_deps="sse4"
aesni_deps="sse42"
avx_deps="sse42" avx_deps="sse42"
xop_deps="avx" xop_deps="avx"
fma3_deps="avx" fma3_deps="avx"
...@@ -6011,6 +6014,7 @@ if enabled x86; then ...@@ -6011,6 +6014,7 @@ if enabled x86; then
echo "3DNow! extended enabled ${amd3dnowext-no}" echo "3DNow! extended enabled ${amd3dnowext-no}"
echo "SSE enabled ${sse-no}" echo "SSE enabled ${sse-no}"
echo "SSSE3 enabled ${ssse3-no}" echo "SSSE3 enabled ${ssse3-no}"
echo "AESNI enabled ${aesni-no}"
echo "AVX enabled ${avx-no}" echo "AVX enabled ${avx-no}"
echo "XOP enabled ${xop-no}" echo "XOP enabled ${xop-no}"
echo "FMA3 enabled ${fma3-no}" echo "FMA3 enabled ${fma3-no}"
......
...@@ -15,6 +15,9 @@ libavutil: 2015-08-28 ...@@ -15,6 +15,9 @@ libavutil: 2015-08-28
API changes, most recent first: API changes, most recent first:
2015-10-27 - xxxxxxx - lavu 55.5.100 - cpu.h
Add AV_CPU_FLAG_AESNI.
2015-10-27 - xxxxxxx - lavc 57.12.100 / 57.8.0 - avcodec.h 2015-10-27 - xxxxxxx - lavc 57.12.100 / 57.8.0 - avcodec.h
Deprecate av_free_packet(). Use av_packet_unref() as replacement, Deprecate av_free_packet(). Use av_packet_unref() as replacement,
it resets the packet in a more consistent way. it resets the packet in a more consistent way.
......
...@@ -118,6 +118,7 @@ int av_parse_cpu_flags(const char *s) ...@@ -118,6 +118,7 @@ int av_parse_cpu_flags(const char *s)
#define CPUFLAG_FMA4 (AV_CPU_FLAG_FMA4 | CPUFLAG_AVX) #define CPUFLAG_FMA4 (AV_CPU_FLAG_FMA4 | CPUFLAG_AVX)
#define CPUFLAG_AVX2 (AV_CPU_FLAG_AVX2 | CPUFLAG_AVX) #define CPUFLAG_AVX2 (AV_CPU_FLAG_AVX2 | CPUFLAG_AVX)
#define CPUFLAG_BMI2 (AV_CPU_FLAG_BMI2 | AV_CPU_FLAG_BMI1) #define CPUFLAG_BMI2 (AV_CPU_FLAG_BMI2 | AV_CPU_FLAG_BMI1)
#define CPUFLAG_AESNI (AV_CPU_FLAG_AESNI | CPUFLAG_SSE42)
static const AVOption cpuflags_opts[] = { static const AVOption cpuflags_opts[] = {
{ "flags" , NULL, 0, AV_OPT_TYPE_FLAGS, { .i64 = 0 }, INT64_MIN, INT64_MAX, .unit = "flags" }, { "flags" , NULL, 0, AV_OPT_TYPE_FLAGS, { .i64 = 0 }, INT64_MIN, INT64_MAX, .unit = "flags" },
#if ARCH_PPC #if ARCH_PPC
...@@ -145,6 +146,7 @@ int av_parse_cpu_flags(const char *s) ...@@ -145,6 +146,7 @@ int av_parse_cpu_flags(const char *s)
{ "3dnow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPUFLAG_3DNOW }, .unit = "flags" }, { "3dnow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPUFLAG_3DNOW }, .unit = "flags" },
{ "3dnowext", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPUFLAG_3DNOWEXT }, .unit = "flags" }, { "3dnowext", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPUFLAG_3DNOWEXT }, .unit = "flags" },
{ "cmov", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CMOV }, .unit = "flags" }, { "cmov", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CMOV }, .unit = "flags" },
{ "aesni" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPUFLAG_AESNI }, .unit = "flags" },
#elif ARCH_ARM #elif ARCH_ARM
{ "armv5te", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV5TE }, .unit = "flags" }, { "armv5te", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV5TE }, .unit = "flags" },
{ "armv6", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV6 }, .unit = "flags" }, { "armv6", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV6 }, .unit = "flags" },
...@@ -205,6 +207,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s) ...@@ -205,6 +207,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
{ "3dnow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOW }, .unit = "flags" }, { "3dnow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOW }, .unit = "flags" },
{ "3dnowext", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOWEXT }, .unit = "flags" }, { "3dnowext", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOWEXT }, .unit = "flags" },
{ "cmov", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CMOV }, .unit = "flags" }, { "cmov", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CMOV }, .unit = "flags" },
{ "aesni", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AESNI }, .unit = "flags" },
#define CPU_FLAG_P2 AV_CPU_FLAG_CMOV | AV_CPU_FLAG_MMX #define CPU_FLAG_P2 AV_CPU_FLAG_CMOV | AV_CPU_FLAG_MMX
#define CPU_FLAG_P3 CPU_FLAG_P2 | AV_CPU_FLAG_MMX2 | AV_CPU_FLAG_SSE #define CPU_FLAG_P3 CPU_FLAG_P2 | AV_CPU_FLAG_MMX2 | AV_CPU_FLAG_SSE
...@@ -340,6 +343,7 @@ static const struct { ...@@ -340,6 +343,7 @@ static const struct {
{ AV_CPU_FLAG_AVX2, "avx2" }, { AV_CPU_FLAG_AVX2, "avx2" },
{ AV_CPU_FLAG_BMI1, "bmi1" }, { AV_CPU_FLAG_BMI1, "bmi1" },
{ AV_CPU_FLAG_BMI2, "bmi2" }, { AV_CPU_FLAG_BMI2, "bmi2" },
{ AV_CPU_FLAG_AESNI, "aesni" },
#endif #endif
{ 0 } { 0 }
}; };
......
...@@ -42,6 +42,7 @@ ...@@ -42,6 +42,7 @@
#define AV_CPU_FLAG_ATOM 0x10000000 ///< Atom processor, some SSSE3 instructions are slower #define AV_CPU_FLAG_ATOM 0x10000000 ///< Atom processor, some SSSE3 instructions are slower
#define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions #define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions
#define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions #define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions
#define AV_CPU_FLAG_AESNI 0x80000 ///< Advanced Encryption Standard functions
#define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used #define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used
#define AV_CPU_FLAG_AVXSLOW 0x8000000 ///< AVX supported, but slow when using YMM registers (e.g. Bulldozer) #define AV_CPU_FLAG_AVXSLOW 0x8000000 ///< AVX supported, but slow when using YMM registers (e.g. Bulldozer)
#define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions #define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions
......
...@@ -56,7 +56,7 @@ ...@@ -56,7 +56,7 @@
*/ */
#define LIBAVUTIL_VERSION_MAJOR 55 #define LIBAVUTIL_VERSION_MAJOR 55
#define LIBAVUTIL_VERSION_MINOR 4 #define LIBAVUTIL_VERSION_MINOR 5
#define LIBAVUTIL_VERSION_MICRO 100 #define LIBAVUTIL_VERSION_MICRO 100
#define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \ #define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \
......
...@@ -126,6 +126,8 @@ int ff_get_cpu_flags_x86(void) ...@@ -126,6 +126,8 @@ int ff_get_cpu_flags_x86(void)
rval |= AV_CPU_FLAG_SSE4; rval |= AV_CPU_FLAG_SSE4;
if (ecx & 0x00100000 ) if (ecx & 0x00100000 )
rval |= AV_CPU_FLAG_SSE42; rval |= AV_CPU_FLAG_SSE42;
if (ecx & 0x01000000 )
rval |= AV_CPU_FLAG_AESNI;
#if HAVE_AVX #if HAVE_AVX
/* Check OXSAVE and AVX bits */ /* Check OXSAVE and AVX bits */
if ((ecx & 0x18000000) == 0x18000000) { if ((ecx & 0x18000000) == 0x18000000) {
......
...@@ -47,6 +47,7 @@ ...@@ -47,6 +47,7 @@
#define X86_FMA3(flags) CPUEXT(flags, FMA3) #define X86_FMA3(flags) CPUEXT(flags, FMA3)
#define X86_FMA4(flags) CPUEXT(flags, FMA4) #define X86_FMA4(flags) CPUEXT(flags, FMA4)
#define X86_AVX2(flags) CPUEXT(flags, AVX2) #define X86_AVX2(flags) CPUEXT(flags, AVX2)
#define X86_AESNI(flags) CPUEXT(flags, AESNI)
#define EXTERNAL_AMD3DNOW(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AMD3DNOW) #define EXTERNAL_AMD3DNOW(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AMD3DNOW)
#define EXTERNAL_AMD3DNOWEXT(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AMD3DNOWEXT) #define EXTERNAL_AMD3DNOWEXT(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AMD3DNOWEXT)
...@@ -69,6 +70,7 @@ ...@@ -69,6 +70,7 @@
#define EXTERNAL_FMA3(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, FMA3) #define EXTERNAL_FMA3(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, FMA3)
#define EXTERNAL_FMA4(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, FMA4) #define EXTERNAL_FMA4(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, FMA4)
#define EXTERNAL_AVX2(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AVX2) #define EXTERNAL_AVX2(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AVX2)
#define EXTERNAL_AESNI(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AESNI)
#define INLINE_AMD3DNOW(flags) CPUEXT_SUFFIX(flags, _INLINE, AMD3DNOW) #define INLINE_AMD3DNOW(flags) CPUEXT_SUFFIX(flags, _INLINE, AMD3DNOW)
#define INLINE_AMD3DNOWEXT(flags) CPUEXT_SUFFIX(flags, _INLINE, AMD3DNOWEXT) #define INLINE_AMD3DNOWEXT(flags) CPUEXT_SUFFIX(flags, _INLINE, AMD3DNOWEXT)
...@@ -91,6 +93,7 @@ ...@@ -91,6 +93,7 @@
#define INLINE_FMA3(flags) CPUEXT_SUFFIX(flags, _INLINE, FMA3) #define INLINE_FMA3(flags) CPUEXT_SUFFIX(flags, _INLINE, FMA3)
#define INLINE_FMA4(flags) CPUEXT_SUFFIX(flags, _INLINE, FMA4) #define INLINE_FMA4(flags) CPUEXT_SUFFIX(flags, _INLINE, FMA4)
#define INLINE_AVX2(flags) CPUEXT_SUFFIX(flags, _INLINE, AVX2) #define INLINE_AVX2(flags) CPUEXT_SUFFIX(flags, _INLINE, AVX2)
#define INLINE_AESNI(flags) CPUEXT_SUFFIX(flags, _INLINE, AESNI)
void ff_cpu_cpuid(int index, int *eax, int *ebx, int *ecx, int *edx); void ff_cpu_cpuid(int index, int *eax, int *ebx, int *ecx, int *edx);
void ff_cpu_xgetbv(int op, int *eax, int *edx); void ff_cpu_xgetbv(int op, int *eax, int *edx);
......
...@@ -772,6 +772,7 @@ BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, ...@@ -772,6 +772,7 @@ BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae,
%assign cpuflags_atom (1<<21) %assign cpuflags_atom (1<<21)
%assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt %assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt
%assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1 %assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1
%assign cpuflags_aesni (1<<24)|cpuflags_sse42
; Returns a boolean value expressing whether or not the specified cpuflag is enabled. ; Returns a boolean value expressing whether or not the specified cpuflag is enabled.
%define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1) %define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)
...@@ -1171,12 +1172,12 @@ AVX_INSTR addsd, sse2, 1, 0, 1 ...@@ -1171,12 +1172,12 @@ AVX_INSTR addsd, sse2, 1, 0, 1
AVX_INSTR addss, sse, 1, 0, 1 AVX_INSTR addss, sse, 1, 0, 1
AVX_INSTR addsubpd, sse3, 1, 0, 0 AVX_INSTR addsubpd, sse3, 1, 0, 0
AVX_INSTR addsubps, sse3, 1, 0, 0 AVX_INSTR addsubps, sse3, 1, 0, 0
AVX_INSTR aesdec, fnord, 0, 0, 0 AVX_INSTR aesdec, aesni, 0, 0, 0
AVX_INSTR aesdeclast, fnord, 0, 0, 0 AVX_INSTR aesdeclast, aesni, 0, 0, 0
AVX_INSTR aesenc, fnord, 0, 0, 0 AVX_INSTR aesenc, aesni, 0, 0, 0
AVX_INSTR aesenclast, fnord, 0, 0, 0 AVX_INSTR aesenclast, aesni, 0, 0, 0
AVX_INSTR aesimc AVX_INSTR aesimc, aesni
AVX_INSTR aeskeygenassist AVX_INSTR aeskeygenassist, aesni
AVX_INSTR andnpd, sse2, 1, 0, 0 AVX_INSTR andnpd, sse2, 1, 0, 0
AVX_INSTR andnps, sse, 1, 0, 0 AVX_INSTR andnps, sse, 1, 0, 0
AVX_INSTR andpd, sse2, 1, 0, 1 AVX_INSTR andpd, sse2, 1, 0, 1
......
...@@ -117,6 +117,7 @@ static const struct { ...@@ -117,6 +117,7 @@ static const struct {
{ "SSSE3", "ssse3", AV_CPU_FLAG_SSSE3|AV_CPU_FLAG_ATOM }, { "SSSE3", "ssse3", AV_CPU_FLAG_SSSE3|AV_CPU_FLAG_ATOM },
{ "SSE4.1", "sse4", AV_CPU_FLAG_SSE4 }, { "SSE4.1", "sse4", AV_CPU_FLAG_SSE4 },
{ "SSE4.2", "sse42", AV_CPU_FLAG_SSE42 }, { "SSE4.2", "sse42", AV_CPU_FLAG_SSE42 },
{ "AES-NI", "aesni", AV_CPU_FLAG_AESNI },
{ "AVX", "avx", AV_CPU_FLAG_AVX }, { "AVX", "avx", AV_CPU_FLAG_AVX },
{ "XOP", "xop", AV_CPU_FLAG_XOP }, { "XOP", "xop", AV_CPU_FLAG_XOP },
{ "FMA3", "fma3", AV_CPU_FLAG_FMA3 }, { "FMA3", "fma3", AV_CPU_FLAG_FMA3 },
......
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